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Lattice New ECP3 FPGA family: Lowest Power, Highest Value, Innovative, In Production!!!
Lattice New ECP3 FPGA family: Lowest Power, Highest Value, Innovative, In Production!!!
The LatticeECP3 family, is the third generation high value FPGA from Lattice Semiconductor, which offers the industry's lowest power consumption and price of any SERDES-capable FPGA device. The LatticeECP3 FPGA family offers multi-protocol 3.2G SERDES with XAUI jitter compliance, DDR3 memory interfaces, powerful DSP capabilities, high density on-chip memory and up to 149K LUTS, all with half the power consumption and half the price of competitive SERDES-capable FPGAs. The entire LatticeECP3 family is manufactured using Fujitsu's advanced low power process technology.
CleanClock™ PLL Performance
·                        Ultra Low Cycle-to-Cycle Jitter (29ps p-p)
·                        Ultra Low Period Jitter (2.5ps)
·                        Low Output to Output Skew (<100ps)
Fully Integrated High-Performance PLL
·                        Programmable lock detect
·                        Four output dividers
·                        Programmable on-chip loop filter
·                        Compatible with spread spectrum clocks
·                        Internal/external feedback
Flexible Clock Reference and External Feedback Inputs
·                        Programmable differential input reference / feedback standards: LVDS, LVPECL, HSTL, SSTL, HCSL
·                        Programmable termination
·                        Clock A/B selection multiplexer
FlexiClock™ I/O
·                        50MHz to 400MHz Input/Output operation
·                        Dual programmable skew per output
·                        Dynamic skew control through I2C
·                        Low output to output skew (<100ps)
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